The present invention relates to an interface for interconnecting Physical Layer (PHY) devices to Link Layer devices with a Packet over SONET (POS) implementation for exchanging packets within a communication system.
The development of protocols for interfaces between PHY devices and Link Layer devices has resulted in a number of specifications such as ATM Forum Utopia Level 2 Specification, the SCI-PHY Level 2 Specification, the SATURN POS-PHY Level 2 Specification and the ATM Forum proposals for Utopia Level 3. Utopia Level 1, Utopia Level 2 and Utopia Level 3 (in its draft form) are used for ATM cell transfer, in either direction, between one or more PHY devices. Utopia Level 1 was designed for data transfer between one PHY device and an ATM Layer device (Link Layer Processing). Utopia Level 2 is an extension of Utopia Level 1 that supports multiple PHY devices. SCI-PHY is a proprietary interface of PMC-Sierra, Inc. similar to Utopia Level 2. Utopia Level 3 is an extension to Utopia Level 1 and 2 that supports point to point transfer at a maximum throughput of 3.2 Gbps.
The foregoing interfaces are based on the transfer of fixed-length packets (cells). The signals and data formats were not designed to handle variable length packets between the data-Link Layer device and the PHY device. Accordingly, there is a need for a standard PHY interface which would provide a versatile bus interface for exchanging variable length packets within a communication system and, at the same time, one which is simple in operation in order to allow forward migration to more elaborate PHY and Link Layer devices.
Accordingly, it is an object of the invention to provide an improved interface for the interconnection of PHY devices to Link Layer devices. It is a further object of the invention to implement a Packet over SONET (POS) technology that provides for the transfer of variable length packets between the data-Link Layer device and the PHY device. It is yet a further object of the invention to provide a standard POS-PHY interface that allows either an 8-bit bus or a 32 bit bus interface running at a maximum speed of 100 MHz.
The present interface, termed the POS-PHY Level 3 interface, is an interface that was developed to cover all application bit rates up to and including 3.2 Gbit/s. It defines the requirements for interoperable single-PHY (one PHY device connects to one Link Layer device) and multi-PHY (multi PHY devices connect to one Link Layer device) applications. It stresses simplicity of operation to allow forward migration to more elaborate PHY and Link Layer devices.
The ATM Forum Utopia Level 2 Specification, the SCI-PHY Level 2 Specification, the SATURN POS-PHY Level 2 Specification and ATM Forum proposals for Utopia Level 3 were used in developing this POS-PHY specification, with several adaptations to support variable packet sizes. However, the POS-PHY specification is not intended to be compatible with the above-mentioned specifications.
This specification defines, firstly, the physical implementation of the POS-PHY bus, secondly, the signaling protocol used to communicate data and, thirdly, the data structure used to store the data into holding FIFO""s.
Going forward, references to xe2x80x9cPOS-PHYxe2x80x9d shall be taken to indicate xe2x80x9cPOS-PHY Level 3xe2x80x9d unless otherwise noted.
The POS-PHY interface defines the interface between SONET/SDH PHY devices and Link Layer devices, which can be used to implement several packet-based protocols like High Level Data Link Control (HDLC) and PPP.
POS-PHY Level 3 specifies the PHY-LINK interface. The Facility Interface (such as SONET OC-3) is defined by several National and International standards organizations including Bellcore and ITU.
The POS-PHY Level 3 specification does not attempt to be compatible to any existing standard. There is no existing equivalent standard. Specifically, POS-PHY does not intend to be compatible with similar ATM specifications like Utopia and SCI-PHY. Although this information is not critical to any implementation, the following bullets highlight the differences between the Utopia/SCI-PHY and POS-PHY interfaces.
Allowance for an 8-bit bus of a 32-bit bus interface running at a maximum speed of 100 MHz. The bus interface is point-to-point (one output driving only one input load).
Byte or double-word (4 bytes) data format that can accommodate variable size packets.
Modification to the RSOC/TSOC start of cell signals to identify the start of packets being transferred over the interface. Renamed the signals to RSOP/TSOP.
Addition of the REOP/TEOP end of packet signals which delineate the end of packets being transferred over the interface.
Addition of the RMOD[1:0]/TMOD[1:0] modulo signals which indicate if the last double-word of the packet transfer contains 1, 2, 3 or 4 valid bytes of data.
Addition of the RERR/TERR error signals which, during the end of the packet, indicate if the transferred packet must be discarded/aborted.
Deletion of the RCA signal. Receive interface of the PHY pushes packet data to the Layer device. Multi-port PHY devices are responsible for performing round-robin servicing of their ports. PHY address is inserted in-band with the packet data.
Transmit interface of the PHY device is selected using an in-band address that is provided on the same bus transferring the packet data.
Addition of the RSX/TSX start of transfer signals which identify when the in-band port address of the PHY is on the RDAT/TDAT bus.
Modification of the TCA cell available signals to form the TPA packet available signals. TPA logic values are defined based on the FIFO fill level (in terms of bytes). In multi-port PHY devices, PHY status indication can be provided either by a polling or a direct status indication scheme. Polled PHY address is provided by a separate address bus and has pipelined timing.
Interface FIFO fill level granularity is byte-based. For the transmit interface FIFO, the packet available status and start of transmission FIFO fill levels are programmable. For the receive interface, the maximum burst transfer size is programmable.
According to the invention there is provided a POS-PHY interface for interfacing between SONET/SDH PHY devices and Link Layer devices, including a 32 bit and an 8-bit point-to-point bus interface having a double-word data format operative to accommodate variable size packets of packet data.
The interface may include a start of cell signal generator operative to generate start of cell signals RSOC/TSOC to identify when an in-band port address of one of the PHY devices is on a bus of the interface.
The interface may have a packet boundary signal generator operative to generate signals REOP/TEOP which delineate the start and end of packets being transferred over the interface.
The interface may include a last double-word valid byte indicator operative to indicate if the last double-word of a packet transfer contains 1, 2, 3, or 4 valid bytes of data.
The interface may have an error signal generator operative to generate REFF/TERR signals at an end of a packet to indicate whether or not a transferred packet should be discarded/aborted.
At least one of the PHY devices may have a plurality of ports with a corresponding respective plurality of first-in first-out buffers (FIFOs) and the one PHY device services each port in a round-robin fashion.
Upon transferring packet data from the Link Layer device to one of a plurality of PHY devices, an address of the one PHY device may be inserted in-band with the packet data.
A transmit interface of one of the PHY devices may be selected using an in-band address provided on a same bus which transfers the packet data.
Transmit packet available signals may be defined based on a byte fill level of first-in first-out buffers of the PHY devices.
The status of packet data reception capacity may be provided using one of polling and direct status indication.
Polled PHY addresses may be provided by a separate address bus and includes pipelined timing.
Transfers of the data units may employ UTOPIA level 2 methods adapted for data transfers of non-constant length.
An in-band port address of a PHY device may be identified when it is on a data transfer bus. Also a start and end of a variable length data transfer may be delineated. The order of relevant bytes in an end of a data transfer may, advantageously, be determined.
In another aspect of the invention, there may be provided a method of interfacing between SONET/SDH PHY devices and Link Layer devices, which includes forming a 32 bit and an 8-bit point-to-point bus interface having a double-word data format operative to accommodate variable size packets of packet data.
The method may include generating start of cell signals RSOC/TSOC to identify when an in-band port address of one of the PHY devices is on a bus of the interface.
REOP/TEOP signals which delineate the start of and end of packets being transferred over the interface may be generated.
The method, preferably, indicates if the last double-word of a packet transfer contains 1, 2, 3, or 4 valid bytes of data. It also includes generating REFF/TERR signals at an end of a packet to indicate whether or not a transferred packet should be discarded/aborted.
At least one of the PHY devices may have a plurality of ports with a corresponding respective plurality of first-in first-out buffers (FIFOs) and the one PHY device services each port in a round-robin fashion. Upon transferring packet data from the Link Layer device to one of a plurality of PHY devices, an address of the one PHY device may be inserted in-band with the packet data.
A transmit interface of one of the PHY devices may be selected using an in-band address provided on a same bus which transfers the packet data.
Transmit packet available signals may be defined based on a byte fill level of first-in first-out buffers of the PHY devices.
The status of packet data reception capacity may be provided using one of polling and direct status indication.
Polled PHY addresses may be provided by a separate address bus and include pipelined timing.